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ltc4260 1 4260f , ltc and lt are registered trademarks of linear technology corporation. allows safe insertion into live backplane 8-bit adc monitors current and voltage i 2 c tm /smbus interface wide operating voltage range: 8.5v to 80v high side drive for external n-channel mosfet input overvoltage/undervoltage protection optional latchoff or autoretry after faults alerts host after faults foldback current limiting available in 24-lead so, 24-lead narrow ssop and 32-lead (5mm 5mm) qfn packages positive high voltage hot swap controller with i 2 c compatible monitoring electronic circuit breakers live board insertion computers, servers hot swap is a trademark of linear technology corporation. i 2 c is a trademark of philips electronics n.v. the ltc ? 4260 hot swap tm controller allows a board to be safely inserted and removed from a live backplane. using an external n-channel pass transistor, the board supply voltage can be ramped up at an adjustable rate. an i 2 c interface and onboard adc allow monitoring of board current, voltage and fault status. the device features adjustable analog foldback current limit with latch off or automatic restart after the ltc4260 remains in current limit beyond an adjustable time-out delay. the controller has additional features to interrupt the host when a fault has occurred, notify when output power is good, detect insertion of a load card and power-up in either the on or off state. uv backplane plug-in card 2.67k * 1.74k 49.9k 48v sda scl alert gnd v dd sense ltc4260 intv cc 100k fdb3632 0.010 ? 10 ? 6.8nf c l 43.5k 3.57k v out 48v 24k 68nf *diodes inc. smbt70a 0.1 f 0.1 f gate timer gnd fb bd_prst adin gpio 4260 ta01 source ov sdao sdai scl alert on connector 1 connector 2 + features descriptio u applicatio s u typical applicatio u v in 50v/div v out 50v/div gpio 5v/div 25ms/div 4260 ta02 i in 2a/div c l = 1000 f power up waveforms 3a, 48v card resident application
ltc4260 2 4260f supply voltages (v dd ) ............................ C 0.3v to 100v input voltages sense ............................ v dd C 10v or C 0.3v to v dd source .......................... gate C 5v to gate + 0.3v bd_prst, fb, on, ov, uv ................... C0.3v to 12v adr0-adr2, timer, adin ..... C0.3v to intv cc + 0.3v scl, sdai ........................................... C0.3v to 6.5v output voltages gpio ................................................... C0.3v to 100v gate (note 3) ..................................... C0.3v to 100v (notes 1, 2) absolute axi u rati gs w ww u package/order i for atio uu w consult ltc marketing for parts specified with wider operating temperature ranges. alert, sdao ........................................... C0.3v to 6.5v supply voltage (intv cc ) ......................... C0.3v to 6.2v operating temperature range ltc4260c ............................................... 0 c to 70 c ltc4260i ............................................. C40 c to 85 c storage temperature range gn, sw packages ............................. C 65 c to 150 c uh package ...................................... C 65 c to 125 c lead temperature (soldering, 10 sec) gn, sw packages only..................................... 300 c 1 2 3 4 5 6 7 8 9 10 11 12 top view gn package 24-lead plastic ssop 24 23 22 21 20 19 18 17 16 15 14 13 sense v dd nc uv ov gnd on scl sdai sdao alert timer gate source nc nc gpio intv cc fb adr2 adr1 adr0 bd_prst adin order part number ltc4260csw ltc4260isw LTC4260CGN ltc4260ign t jmax = 125 c, ja = 85 c/w 1 2 3 4 5 6 7 8 9 10 11 12 top view sw package 24-lead plastic so 24 23 22 21 20 19 18 17 16 15 14 13 sense v dd nc nc uv gnd on scl sdai sdao alert timer gate source nc nc gpio intv cc fb adr2 adr1 adr0 bd_prst adin order part number t jmax = 125 c, ja = 75 c/w 32 31 30 29 28 27 26 25 9 10 11 12 top view 33 uh package 32-lead (5mm 5mm) plastic qfn 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1 nc nc nc uv ov gnd on scl nc nc nc nc gpio intv cc fb adr2 v dd v ddk sense nc nc nc gate source sdai sdao alert timer adin bd_prst adr0 adr1 t jmax = 125 c, ja = 34 c/w exposed pad (pin 33) pcb electrical connection optional order part number ltc4260cuh ltc4260iuh uh part marking electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v dd = 48v, unless otherwise noted. 4260 symbol parameter conditions min typ max units general v dd input supply range 8.5 80 v i dd input supply current 25 ma v dd(uvl) v dd supply undervoltage lockout v dd falling 7 7.45 7.9 v
ltc4260 3 4260f electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v dd = 48v, unless otherwise noted. symbol parameter conditions min typ max units intv cc(uvl) v cc supply undervoltage lockout intv cc falling 3.4 3.8 4.2 v intv cc internal regulator voltage 5 5.5 6 v gate drive t d turn-on delay 50 100 150 ms ? v gate external n-channel gate drive v dd = 20v to 80v 10 14 18 v (v gate C v source )v dd = 8.5v to 20v 4.5 6 18 v i gate(up) external n-channel pull-up current gate drive on, v gate = 0v C14 C18 C22 a i gate(fst) external n-channel fast pull-down fast turn off, v gate = 48v, v source = 38v 400 600 1000 ma i gate(dn) external n-channel pull-down current gate drive off, v gate = 58v, v source = 48v 0.7 1 1.4 ma i source source pin input current source = 48v 200 400 600 a input pins v on(th) on pin threshold voltage v on rising 1.19 1.235 1.27 v ? v on(hyst) on pin hysteresis 60 130 200 mv i on(in) on pin input current v on = 1.2v 0 1 a v ov(th) ov pin threshold voltage v ov rising 3.43 3.5 3.56 v ? v ov(hyst) ov pin hysteresis 70 90 120 mv i ov(in) ov pin input current v ov = 3.5v 0 1 a v uv(th) uv pin threshold voltage v uv rising 3.43 3.5 3.56 v ? v uv(hyst) uv pin hysteresis 310 380 440 mv i uv(in) uv pin input current v uv = 3.5v 0 2 a v uv(rth) uv pin reset threshold voltage v uv falling 1.18 1.235 1.27 v ? v uv(rhyst) uv pin reset threshold hysteresis 80 160 250 mv ? v sense(th) current limit sense voltage threshold v fb = 3.5v 40 50 60 mv (v dd C v sense )v fb = 0v 10 20 30 mv i sense(in) sense pin input current v sense = 48v 70 100 130 a v fb foldback pin power good threshold fb rising 3.43 3.5 3.56 v ? v fb(hyst) fb pin power good hysteresis 80 100 120 mv i fb foldback pin input current fb = 3.5v 0 2 a v bd_prst(th) bd_prst input threshold v bd_prst rising 1.2 1.235 1.27 v ? v bd_prst(hyst) bd_prst hysteresis 70 130 190 mv i bd_prst bd_prst pullup current bd_prst = 0v C7 C10 C16 a v gpio(th) gpio pin input threshold v gpio rising 1.6 1.8 2 v ? v gpio(hyst) gpio pin hysteresis 80 mv v gpio(ol) gpio pin output low voltage i gpio = 2ma 0.25 0.5 v i gpio(in) gpio pin input leakage current v gpio = 80v 0 10 a r adin adin pin input resistance v adin = 1.28v 210 m ? i adin adin pin input current v adin = 2.56v 0 1 a timer v timer(h) timer pin high threshold v timer rising 1.2 1.235 1.28 v v timer(l) timer pin low threshold v timer falling 0.1 0.2 0.3 v i timer(up) timer pin pull-up current v timer = 0v C80 C100 C120 a i timer(dn) timer pin pull-down current v timer = 1.3v 1.4 2 2.6 a i timer(ratio) timer pin current ratio 1.6 2 2.7 % i timer(dn) /i timer(up)
ltc4260 4 4260f electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v dd = 48v, unless otherwise noted. symbol parameter conditions min typ max units ac parameters t plh(gate) input high (on) to gate high c gate = 1pf 13 s propagation delay t phl(gate) input high (ov, bd_prst), input low c gate = 1pf 0.5 3 s (on, uv) to gate low propagation delay t phl(sense) (v dd C sense) high to gate low v dd C sense = 200mv, c gate = 10nf 0.4 1 s adc resolution (no missing codes) (note 4) 8 bits integral nonlinearity v dd C sense (note 5) C2 0.5 2 lsb source C1.25 0.2 1.25 lsb adin C1.25 0.2 1.25 lsb offset error v dd C sense C1.5 1.5 lsb source C1 1 lsb adin C1 1 lsb 1lsb step size v dd C sense (note 6) 292 300 308 v source 392 400 408 mv adin 9.8 10 10.2 mv full-scale voltage v dd C sense (note 7) 74.9 76.8 78.7 mv source 100.4 102.4 104.4 v adin 2.51 2.560 2.61 v conversion rate 10 hz i 2 c interface v adr(h) adr0 to adr2 input high voltage intv cc intv cc intv cc v threshold C 0.6 C 0.45 C 0.25 v adr(l) adr0 to adr2 input low voltage threshold 0.25 0.45 0.65 v i adr(in) adr0 to adr2 input current adr0 to adr2 = 0v, 5.5v C80 80 a v sdai,scl(th) sdai, scl input threshold 1.6 1.8 2 v i sdai,scl(in) sdai, scl input current scl, sdai = 5v 0 1 a v sdao(ol) sdao output low voltage i sdao = 5ma 0.2 0.4 v v alert(ol) alert output low voltage i alert = 5ma 0.2 0.4 v i sdao,alert(in) sdao, alert input current sdao, alert = 5v 0 1 a i 2 c interface timing (note 4) f scl(max) maximum scl clock frequency operates with f scl f scl(max) 400 khz t buf(min) minimum bus free time between 0.12 1.3 s stop/start condition t su,sta(min) minimum repeated start condition 30 600 ns set-up time t hd,sta(min) minimum hold time after (repeated) start 140 600 ns condition t su,sto(min) minimum stop condition set-up time 30 600 ns t su,dat(min) minimum data set-up time input 30 100 ns t hd,dati(min) minimum data hold time input C100 0 ns t hd,dato(min) minimum data hold time output 300 500 900 ns t sp(max) maximum suppressed spike pulse width 50 110 250 ns c x scl, sda input capacitance sdai tied to sdao 5 10 pf note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: all currents into pins are positive, all voltages are referenced to gnd unless otherwise specified.
ltc4260 5 4260f electrical characteristics typical perfor a ce characteristics uw i dd vs v dd v dd (v) 0 i dd (ma) 2.0 85 c 25 c 2.5 80 4260 g01 1.5 1.0 20 40 60 100 3.0 C40 c temperature ( c) C50 3.46 uv low-high threshold (v) 3.48 3.50 3.52 3.54 C25 0 25 50 4260 g02 75 100 temperature ( c) C50 0.34 uv hysteresis (v) 0.35 0.36 0.37 0.38 0.39 C25 02550 4260 g03 75 100 uv low-high threshold vs temperature uv hysteresis vs temperature on, bd_prst low-high threshold vs temperature temperature ( c) C50 1.220 on, bd_prst low-high threshold (v) 1.225 1.230 1.235 1.240 1.245 C25 02550 4260 g04 75 100 on, bd_prst hysteresis vs temperature temperature ( c) C50 0.10 on, bd_prst hysteresis (v) 0.11 0.12 0.13 0.14 0.16 C25 02550 4260 g05 75 100 0.15 t a = 25 c, v dd = 48v unless otherwise noted. note 3: limits on maximum rating is defined as whichever limit occurs first. an internal clamp limits the gate pin to a minimum of 10v above source. driving this pin to voltages beyond the clamp may damage the device. note 4: guaranteed by design and not subject to test. note 5: integral nonlinearity is defined as the deviation of a code from a precise analog input voltage. maximum specifications are limited by the lsb step size and the single shot measurement. typical specificatons are measured from the 1/4, 1/2 and 3/4 areas of the quantization band. note 6: 1lsb step size specification is guaranteed by full-scale voltage measurement and by design. note 7: full-scale current sense specification corresponds to code 200. codes above 200 may be discarded by offset cancellation. int v cc vs i load i load (ma) 0 0 intv cc (v) 1 2 3 4 C4 C8 4260 g18 5 6 C2 C6 C10 v dd = 48v v dd = 12v caution: drawing current from intv cc increases power dissipation and t j
ltc4260 6 4260f typical perfor a ce characteristics uw current limit sense voltage vs fb voltage current limit propagation delay vs sense voltage i gate pull up vs temperature t a = 25 c, v dd = 48v unless otherwise noted. fb voltage (v) 0 0 current limit sense voltage (v dd C v sense ) (mv) 10 20 30 40 12 3 4 4260 g07 50 60 0.5 1.5 2.5 3.5 current limit sense voltage (v dd C v sense ) (mv) 0 0.1 current limit propagation delay ( s) 1 10 100 1000 50 100 150 200 4260 g08 250 300 350 temperature ( c) C50 C10 i gate pull up ( a) C15 C20 C25 C25 0 25 50 4260 g09 75 100 gate drive vs i gate gate drive vs temperature i gate ( a) 0 gate drive (v gate C v source ) (v) 8 10 12 C20 4260 g10 6 4 0 C5 C10 C15 2 16 14 v dd = 80v v dd = 48v v dd = 12v gate drive vs v dd v dd (v) 5 gate drive (v gate C v source ) (v) 12 14 16 20 30 4260 g11 10 8 10 15 25 35 85 c 25 c C40 c 40 6 4 temperature ( c) C50 11 gate drive (v gate C v source ) (v) 12 13 14 15 16 C25 02550 4260 g12 75 100 adc total unadjusted error vs code (adin pin) code 0 adc total unadjusted error (lsb) 0 1 256 4260 g14 C1 C2 64 128 192 2 timer pull-up current vs temperature temperature ( c) C50 C90 timer pull-up current ( a) C95 C100 C105 C110 C25 0 25 50 4260 g06 75 100 gpio v out low vs i load i load (ma) 0 14 12 10 8 6 4 2 0 30 50 4260 g13 10 20 40 60 gpio v out low (v)
ltc4260 7 4260f uu u pi fu ctio s adin: adc input. a voltage between 0v and 2.56v applied to this pin can be measured by the onboard adc. tie to ground if unused. adr0 to adr2: serial bus address inputs. tying these pins to ground, open or intv cc configures one of 27 pos- sible addresses. see table 1 in applications information. alert: fault alert output. open-drain logic output that can be pulled to ground when a fault occurs to alert the host controller. a fault alert is enabled by the alert register. this device is compatible with smbus alert protocol. see applications information. tie to ground if unused. bd_prst: board present input. ground this pin to enable the n-channel fet to turn on after 100ms debounce delay. when this pin is high, the fet is off. an internal 10 a current source pulls up this pin. transitions on this pin will be recorded in the fault register. a high-to-low transition activates the logic to read the state of the on pin and clear faults. see applications information. exposed pad (pin 33, uh package): exposed pad may be left open or connected to device ground. fb: foldback and power good input. a resistive divider from the output voltage is tied to this pin. when the voltage at this pin drops below 3.41v, the output power is consid- ered bad and the current limit is reduced. the power bad condition can be indicated with the gpio pin and a power bad fault can be logged in this condition. see applications information. gate: gate drive for external n-channel fet. an internal 18 a current source charges the gate of the external n-channel mosfet. a resistor and capacitor network from this pin to ground sets the turn-on rate and compen- sates the active current limit. during turn-off there is a 1ma pull-down current. during a short circuit or under- voltage lockout (v dd or intv cc ), a 600ma pull-down current source between gate and source is activated. gnd: device ground. typical perfor a ce characteristics uw t a = 25 c, v dd = 48v unless otherwise noted. adc inl vs code (adin pin) code 0 adc inl (lsb) 0 0.25 256 4260 g16 C0.25 C0.50 64 128 192 0.50 adc dnl vs code (adin pin) code 0 adc dnl (lsb) 0 0.25 256 4260 g17 C0.25 C0.50 64 128 192 0.50 adc full-scale error vs temperature (adin pin) temperature ( c) C50 C2 adc full-scale error (lsb) C1 0 1 2 C25 0 25 50 3708 g15 75 100
ltc4260 8 4260f gpio: general purpose input/output. open-drain logic output and logic input. defaults to pull low to indicate power is bad. configure according to table 3. nc: no connect. unconnected pins. these pins provide extra distance between high and low voltage pins. on: on control input. a rising edge turns on the external n-channel fet and a falling edge turns it off. this pin is also used to configure the state of the fet on bit (and hence the external fet) at power up. for example if the on pin is tied high, then the fet on control bit (a3) will go high 100ms after power-up. likewise if the on pin is tied low then the part will remain off after power-up until the fet on control bit is set high using the i 2 c bus. a high-to-low transition on this pin will clear faults. ov (gn/uh packages): overvoltage comparator input. connect this pin to an external resistive divider from v dd . if the voltage at this pin rises above 3.5v, an overvoltage fault is detected and the switch turns off. tie to gnd if unused. scl: serial bus clock input. data at the sda pin is shifted in or out on rising edges of scl. this is a high impedance pin that is generally driven by an open-collector output from a master controller. an external pull-up resistor or current source is required. sdai: serial bus data input. a high impedance input used for shifting in address, command or data bits. normally tied to sdao to form the sda line. sdao: serial bus data output. open-drain output used for sending data back to the master controller or acknowledg- ing a write operation. normally tied to sdai to form the sda line. an external pull-up resistor or current source is required. sense: current sense input. connect this pin to the output of the current sense resistor. the current limit circuit controls the gate pin to limit the sense voltage between the v dd and sense pins to 50mv or less depend- ing on the voltage at the fb pin. this pin is used as an input to the 8-bit adc. source: n-channel mosfet source connection and adc input. connect this pin to the source of the external n-channel mosfet switch. this pin also serves as the adc input to monitor output voltage. the pin provides a return for the gate pull-down circuit and as a supply for the charge pump circuit. timer: timer input. connect a capacitor between this pin and ground to set a 12ms/ f duration for current limit before the switch is turned off. the duration of the off time is 518ms/ f when autoretry during current limit is enabled. a minimum value of 0.1nf must be connected to this pin. uv: undervoltage comparator input. connect this pin to an external resistive divider from v dd . if the voltage at this pin falls below 3.12v, an undervoltage fault is detected and the switch turns off. pulling this pin below 1.2v resets all faults and allows the switch to turn back on. tie to intv cc if unused. v dd : supply voltage and current sense input. this pin has an undervoltage lockout threshold of 7.45v. intv cc : internal low voltage supply decoupling output. connect a 0.1 f capacitor from this pin to ground. this pin can be used to drive the other pins to logic high and has an undervoltage lockout threshold of 3.8v. v ddk (uh package): same as v dd . connect this pin to v dd . v ddk tied to v dd internally with 18 ? . uu u pi fu ctio s
ltc4260 9 4260f fu ctio al diagra u u w C + uv 3.5v uvs ovs reset ons v dd uvlo 3.5v 1.235v 1.235v intv cc 1.235v 7.45v source i 2 c v dd C sense 5 i 2 c addr uv C + ov 3.5v C + 2v pwrgd fet on C + pg C + rst C + bp board present C + C + C + 1.235v C + 0.2v logic tm2 uvlo2 C + C + on uvlo1 fb ov gn/uh only bd_prst on 10 a sdai sdao scl alert adr0 adr1 adr2 gnd uh only exposed pad v dd adin 1 of 27 8 3.8v v cc uvlo 4260 bd intv cc timer gpio intv cc v dd 100 a 1.8v 2 a a/d converter 5.5v gen tm1 source gate C + cs v ddk v dd 18 ? sense uh only internal power charge pump and gate driver foldback 20mv to 50mv gp + C
ltc4260 10 4260f operatio u the functional diagram displays the main functional areas of this device. the ltc4260 is designed to turn a boards supply voltage on and off in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. during normal operation, the charge pump and gate driver turn on the external n-channel pass fets gate to pass power to the load. the gate driver uses a charge pump that derives its power from the source pin. when the source pin is at ground, the charge pump is powered from an internal 12v supply derived from v dd . this results in a 200 a current load on the source pin when the gate is up. also included in the gate driver is an internal 15v gate-to-source clamp. the current sense (cs) amplifier monitors the load current using the difference between the v dd and sense pin voltage. the cs amplifier limits the current in the load by reducing the gate-to-source voltage in an active con- trol loop. the cs amplifier requires 100 a input bias current from both the v dd and the sense pins. a short circuit on the output to ground causes significant power dissipation during active current limiting. to limit this power, the foldback amplifier reduces the current limit value from 50mv to 20mv (referred to the v dd minus sense voltage) in a linear manner as the fb pin drops below 2v (see typical performance curves). if an overcurrent condition persists, the timer pin ramps up with a 100 a current source until the pin voltage exceeds 1.2v (comparator tm2). this indicates to the logic that it is time to turn off the pass fet to prevent overheating. at this point the timer pin ramps down using the 2 a current source until the voltage drops below 0.2v (comparator tm1) which tells the logic that the pass transistor has cooled and it is safe to turn it on again. the output voltage is monitored using the fb pin and the pg comparator to determine if the power is available for the load. the power good condition is signalled by the gpio pin using an open-drain pull-down transistor. the gpio pin can also be used as a general purpose input (gp comparator) or output pin. the functional diagram shows the monitoring blocks of the ltc4260. the group of comparators on the left side includes the uv, ov, rst, bp and on comparators. these comparators are used to determine if the external condi- tions are valid prior to turning on the fet. but first the two undervoltage lockout circuits uvlo1 and uvlo2 must validate the input supply and the internally generated 5.5v supply (intv cc ) and generate the power up initialization to the logic circuits. included in the ltc4260 is an 8-bit a/d converter. the converter has a 3-input mux to select between the adin pin, the source pin and the v dd C sense voltage. an i 2 c interface is provided to read the a/d registers. it also allows the host to poll the device and determine if faults have occurred. if the alert line is used as an interrupt, the host can respond to a fault in real time. the typical sda line is divided into an sdai (input) and sdao (output). this simplifies applications using an optoisolator driven directly from the sdao output. the i 2 c device address is decoded using the adr0, adr1 and adr2 pins. these inputs have three states each that decode into a total of 27 device addresses. ti i g diagra u ww t su, dat t su, sto t su, sta t buf t hd, sta t sp t sp t hd, dato, t hd, dati t hd, sta start condition stop condition repeated start condition start condition 4260 td01 sdai/sdao scl
ltc4260 11 4260f applicatio s i for atio wu uu the typical ltc4260 application is in a high availability system that uses a positive voltage supply to distribute power to individual cards. the device measures card voltages and currents and records past and present fault conditions. the system queries each ltc4260 over the i 2 c periodically and reads the stored information. the basic ltc4260 application circuit is shown in fig- ure 1. external component selection is discussed in detail in the design example section. turn-on sequence the power supply on a board is controlled by placing an external n-channel pass transistor (q1) in the power path. note that sense resistor (r s ) detects current and capacitor c1 controls the gate slew rate. resistor r6 compensates the current control loop while r5 prevents high frequency oscillations in q1. resistors r1, r2 and r3 provide undervoltage and overvoltage sensing. several conditions must be present before the external switch can be turned on. first the external supply v dd must exceed its undervoltage lockout level. next the internally generated supply intv cc must cross its 4.5v undervoltage threshold. this generates a 60 s to 120 s power-on-reset pulse. during reset the fault registers are cleared and the control registers are set or cleared as described in the register section. after the power-on-reset pulse, the ltc4260 will go through the following turn-on sequence. first, the uv and ov pins must indicate that the input power is within the acceptable range and the bd_prst pin must be pulled low. all of these conditions must be satisfied for duration of 100ms to ensure that any contact bounce during insertion has ended. when these initial conditions are satisfied, the on pin is checked. if it is high, the external switch turns on. if it is low, the external switch turns on when the on pin is brought high or if a serial bus turn-on command is received. the switch is turned on by charging up the gate with a 18 a current source (figure 2). the voltage at the gate pin rises with a slope equal to 18 a/c1 and the supply inrush current is set at: i c c a inrush l = 1 18 ? when the gate voltage reaches the fet threshold voltage, the switch begins to turn on and the source voltage follows the gate voltage as it increases. 16 uv r3 2.67k 1% r2 1.74k 1% 5 42 1 24 23 18 13 20 14 7 9 10 8 11 r1 49.9k 1% z1* smbt70a v dd sense ltc4260gn r6 100k q1 fdb3632 r s 0.010 ? v in 48v r5 10 ? c1 6.8nf c l 330 f r7 43.5k 1% v out 48v r8 3.57k 1% r4 100k c f 0.1 f gate intv cc adr0 adr1 nc adr2 gnd fb bd_prst timer adin gpio 4260 f01 source ov on sdai sda0 scl alert 12 19 15 c3 0.1 f 17 6 + c t 68nf *diodes, inc backplane plug-in card sda scl alert gnd connector 1 connector 2 figure 1. 5a, 48v card resident application
ltc4260 12 4260f applicatio s i for atio wu uu as the source voltage rises, so will the fb pin which is monitoring it. if the voltage across the current sense resistor r s gets too high, the inrush current will then be limited by the internal current limit circuitry. once the fb pin crosses its 3.5v threshold, the gpio pin, in its default configuration, will cease to pull low and indicate that the power is now good. turn-off sequence the switch can be turned off by a variety of conditions. a normal turn-off is initiated by the on pin going low or a serial bus turn-off command. additionally, several fault conditions will turn off the switch. these include an input overvoltage (ov pin), input undervoltage (uv pin), over- current circuit breaker (sense pin) or bd_prst going high. writing a logic one into the uv, ov or overcurrent fault bits will also turn off the switch if their autoretry bits are set to false. normally the switch is turned off with a 1ma current pulling down the gate pin to ground. with the switch turned off, the source voltage drops and when the fb pin crosses below its threshold, gpio pulls low to indicate that the output power is no longer good. if the v dd pin falls below 7.5v for greater than 5 s or intv cc drops below 3.8v for greater than 1 s, a fast shutdown of the switch is initiated. the gate pin is pulled down with a 600ma current to the source pin. overcurrent fault the ltc4260 features an adjustable current limit with foldback that protects against short circuits or excessive load current. to protect against excessive power dissipa- tion in the switch during active current limit, the available current is reduced as a function of the output voltage sensed by the fb pin. the device also features a variable overcurrent response time. a graph in the typical perfor- mance curves shows the delay from a voltage step at the sense pin until the gate voltage starts falling, as a function of overdrive. an overcurrent fault occurs when the current limit circuitry has been engaged for longer than the time-out delay set by the timer pin. current limiting begins when the current sense voltage between the v dd and sense pins reaches 20mv to 50mv (depending on the foldback). the gate pin is then brought down with a 600ma gate-to-source current. the voltage on the gate is regulated in order to limit the current sense voltage to less than 50mv. at this point, a circuit breaker time delay starts by charging the external timing capacitor from the timer pin with a 100 a pull-up current. if the timer pin reaches its 1.2v thresh- old, the external switch turns off (with a 1ma current from gate to ground). the overcurrent present bit, c2, and the overcurrent fault bit, d2, are set at this time. the circuit breaker time delay is given by: t cb = c t ? 12 [ms/ f] after the switch is turned off, the timer pin begins discharging the timing capacitor with a 2 a pull-down current. when the timer pin reaches its 0.2v threshold, the overcurrent present bit, c2, is cleared, and the switch will be allowed to turn on again if the overcurrent fault has been cleared. however, if the overcurrent autoretry bit, a2, has been set then the switch turns on again automati- cally (without resetting the overcurrent fault). use a mini- mum value of 0.1nf for c t . the waveform in figure 3 shows how the output latches off following a short circuit. the drop across the sense resistor is held at 20mv as the timer ramps up. figure 2. supply turn-on v dd + 13v v dd 4260 f02 t 1 t 2 gate v out slope = 18 a/c1
ltc4260 13 4260f applicatio s i for atio wu uu undervoltage autoretry has been disabled by clearing bit a1. when power is applied to the device, if uv is below its 3.12v threshold after intv cc crosses its 4.5v undervolt- age lockout threshold, an undervoltage fault will be logged in the fault register. board present change of state whenever the bd_prst pin toggles, bit d4 is set to indicate a change of state. when the bd_prst pin goes high, indicating board removal, the switch turns off imme- diately (with a 1ma current from gate to ground) and clears the board present bit, c4. if the bd_prst pin is pulled low, indicating a board insertion, all fault bits except d4 will be cleared and the board present bit, c4, is set. if the bd_prst pin remains low for 100ms the state of the on pin will be captured in the fet on control bit a3. this turns the switch on if the on pin is tied high. there is an internal 10 a pull-up current source on the bd_prst pin. if the system shuts down due to a fault, it may be desirable to restart the system simply by removing and reinserting a load card. in cases where the ltc4260 and the switch reside on a backplane or midplane and the load resides on a plug-in card, the bd_prst pin can be used to detect when the plug-in card is removed (see figure 4). once the plug-in card is reinserted the fault register is cleared (except for d4). after 100ms the state of the on pin is latched into bit a3 of the control register. at this point the system will start up again. if a connection sense on the plug-in card is driving the bd_prst pin, the insertion or removal of the card may cause the pin voltage to bounce. this will result in clearing the fault register when the card is removed. the pin can be debounced using a filter capacitor, c bd_prst , on the bd_prst pin as shown in figure 4. the filter time is given by: t filter = c bd_prst ? 123 [ms/ f] fet short fault a fet short fault will be reported if the data converter measures a current sense voltage greater than or equal to 2mv while the fet is turned off. this condition sets the fet short present bit, c5, and the fet short fault bit d5. figure 3. short-circuit waveforms v out 50v/div i out 5a/div ? v gate 10v/div timer 2v/div 100 s/div 4260 f03 during a short circuit, if the current limit sense voltage exceeds 150mv, the active current limit enters a high current protection mode that immediately turns off the output transistor by pulling the gate-to-source voltage to zero. current in the output transistor drops from tens of amps to zero in a few hundred nanoseconds. the input voltage will drop during the high current and then spike upwards due to parasitic inductances when the fet shuts off (see supply transients). following this event, the part may turn on again after a delay (typically the 100ms normal turn-on delay if the input voltage drops below the uvlo threshold) and enters active current limit before shutting off. overvoltage fault an overvoltage fault occurs when the ov pin rises above its 3.5v threshold. this shuts off the switch immediately (with a 1ma current from gate to ground) and sets the overvoltage present bit, c0, and the overvoltage fault bit d0. if the ov pin subsequently falls back below the threshold for 100ms, the switch will be allowed to turn on again unless the overvoltage autoretry has been disabled by clearing bit a0. undervoltage fault an undervoltage fault occurs when the uv pin falls below its 3.12v threshold. this turns off the switch immediately (with a 1ma current from gate to ground) and sets the undervoltage present bit, c1, and the undervoltage fault bit d1. if the uv pin subsequently rises above the threshold for 100ms, the switch will turn on again unless the
ltc4260 14 4260f applicatio s i for atio wu uu power bad fault a power bad fault will be reported if the fb pin drops below its 3.41v threshold while the fet is on. this pulls the gpio pin low immediately, when configured as pwrgd, and sets the power bad present bit, c3, and the power bad fault bit d3. a circuit will prevent a power bad fault if the gate- to-source voltage is low, eliminating false power bad faults during power-up or power-down. if the fb pin subsequently rises back above the threshold, the gpio pin will return to a high impedance state and bit c3 will be cleared. fault alerts when any of the fault bits in fault register d are set, an optional i 2 c bus alert can be generated by setting the appropriate bit in the alert register b. this allows only selected faults to generate alerts. at power-up the default state is to not alert on faults. if an alert is enabled, the corresponding fault will cause the alert pin to pull low. after the bus master controller broadcasts the alert re- sponse address, the ltc4260 responds with its address on the sda line and releases alert as shown in figure 11. if there is a collision between two ltc4260s responding with their addresses simultaneously, then the device with the lower address wins arbitration and responds first. the alert line will also be released if the device is addressed by the bus master. once the alert signal has been released for one fault, it will not be pulled low again until the fault register indicates a different fault has occurred or the original fault is cleared and it occurs again. note that this means repeated or continuing faults will not generate alerts until the associated fault register bit has been cleared. resetting faults faults are reset with any of the following conditions. first, a serial bus command writing zeros to the fault register d will clear the associated faults. second, the entire fault register is cleared when the switch is turned off by either the on pin or bit a3 going from high to low, or if the uv pin is brought below its 1.23v reset threshold, or if intv cc falls below its 3.8v undervoltage lockout threshold. fi- nally, when bd_prst is brought from high to low, only fault bits d0-d3 and d5 are cleared, the bit d4 that indicates a bd_prst change of state will be set. faults that are still present (as indicated in the status register c) cannot be cleared. the fault register will not be cleared when autoretrying. when autoretry is disabled the existence of a d0, d1 or d2 fault keeps the switch off. as soon as the fault is cleared, the switch will turn on. if autoretry is enabled, then a high value in c0, c1 or c2 will hold the switch off and the fault register is ignored. subsequently, when the c0, c1 and c2 bits are cleared, the switch is allowed to turn on again data converter the ltc4260 incorporates an 8-bit data converter that continuously monitors three different voltages. the source pin uses a 1/40 resistive divider to monitor a full- scale voltage of 102.4v with 0.4v resolution (divider converts 102.4v to 2.56v). the adin pin is monitored with a 2.56v full scale and 10mv resolution, and the voltage between the v dd and sense pins is monitored with a 76.8mv full scale and 300 v resolution. the results from each conversion are stored in registers e, f and g and are updated 10 times per second. setting control register bit a5 invokes a test mode that halts the data converter updates so that registers e, f and g can be written to and read from for software testing. C + 1.235v gnd motherboard connector plug-in card source out ltc4260 10 a 23 6 bd_prst 14 c bd_prst load 4260 f04 figure 4. plug-in card insertion/removal
ltc4260 15 4260f gate pin voltage a curve of gate drive vs v dd is shown in the typical performance curves. at the minimum input supply volt- age of 8.5v, the minimum gate drive voltage is 4.5v. when the input supply voltage is higher than 20v, the gate drive is at least 10v and a regular n-fet can be used. in applications over a 8.5v to 20v range, a logic level n-fet must be used to maintain adequate gate enhancement. the gate pin is clamped at a typical value of 15v above the source pin. configuring the gpio pin table 3 describes the possible states of the gpio pin using the control register bits a6 and a7. at power-up, the default state is for the gpio pin to go high impedance when power is good (fb pin greater than 3.5v). other uses for the gpio pin are to pull down when power is good, a general purpose output and a general purpose input. compensating the active current loop the active current limit circuit is compensated using the resistor r6 and the slew rate capacitor c1. the value for c1 is calculated to limit the inrush current. the suggested value for r6 is 100k. this value should work for most pass fets (q1). if the gate capacitance of q1 is very small then the best method to compensate the loop is to add a 10nf capacitor between the gate and source terminals. supply transients the ltc4260 is designed to ride through supply transients caused by load steps. if there is a shorted load and the parasitic inductance back to the supply is greater than 0.5 h, there is a chance that the supply could collapse before the active current limit circuit brings down the gate pin. in this case the undervoltage monitors turn off the pass fet. the undervoltage lockout circuit has a 5 s filter time after v dd drops below 7.5v. the uv pin reacts in 2 s to shut the gate off, but it is recommended to add a filter capacitor c f to prevent unwanted shutdown caused by short transient. eventually either the uv pin or the undervoltage lockout responds to bring the current under control before the supply completely collapses. supply transient protection the ltc4260 is 100% tested and guaranteed to be safe from damage with supply voltages up to 100v. however, spikes above 100v may damage the part. during a short- circuit condition, the large change in currents flowing through the power supply traces can cause inductive voltage spikes which could exceed 100v. to minimize the spikes, the power trace inductance should be minimized by using wider traces or heavier trace plating. adding a snubber circuit will dampen the voltage spikes. it is built using a 100 ? resistor in series with a 0.1 f capacitor between v dd and gnd. a surge suppressor, z1 in figure 1, at the input will clamp the voltage spikes. design example as a design example, take the following specifications: v in = 48v, i max = 5a, i inrush = 1a, c l = 330 f, v uvon = 43v, v uvoff = 38.5v, v ovoff = 70v, v pwrgdup = 46v, v pwrgddn = 45v and i 2 c address = 1010011. the selection of the sense resistor, r s , is set by the overcurrent threshold of 50mv: r mv i mv a s max === ? 50 50 5 0 010 . the fet should be sized to handle the power dissipation during the inrush charging of the output capacitor c out . the method used to determine the power is the principle: e c = energy in c l = energy in q1 thus: e c = 1/2 cv 2 = 1/2(0.33mf)(48v) 2 = 0.38j calculate the time it takes to charge up c out : t cv i fv a ms chargup lin inrush == = ?? 330 48 1 16 the average power dissipated in the fet: p e t j ms w diss c chargup == ? 038 16 24 . applicatio s i for atio wu uu
ltc4260 16 4260f the soa (safe operating area) curves of candidate fets must be evaluated to ensure that the heat capacity of the package can stand 24w for 16ms. the soa curves of the fairchild fdb3632 provide for 1a at 50v (50w) for 10ms, satisfying the requirement. the inrush current is set to 1a using c1: cc i i mf a a nf l gate up inrush 1033 18 1 59 == = () .. default values of r5 = 10 ? and r6 = 100k are chosen as discussed previously. the power dissipated in the fet during overcurrent must be limited. the active current limit uses a timer to prevent excessive energy dissipation in the fet. the worst-case power occurs when the voltage versus current profile of the foldback current limit is at the maximum. this occurs when the current is 5a and the voltage is 1/2 of the 48v or 24v. see the current limit sense voltage vs fb voltage in the typical performance curves to view this profile. in order to survive 120w, the fet soa curve dictates the maximum time at this power level. this particular fet allows 300w at 1ms or less. therefore, it is acceptable to set the current limit timeout using c t to be 0.81ms: c ms ms f nf t = [] = 081 12 68 . / note the minimum value for c t is 0.1nf. choose r1, r2, r3, r7 and r8 for the uv, ov and pg threshold voltages: v ovrising = 71.2v, v ovfalling = 69.44v (using v ov(th) = 3.5v rising and 3.41v falling) v uvrising = 43v, v uvfalling = 38.5v, (using v uv(th) = 3.5v rising and 3.12v falling) v pgrising = 46.14v, v pgfalling = 45v, (using v fb = 3.5v rising and 3.411v falling) in addition a 0.1 f ceramic bypass capacitor is placed on the intv cc pin. the complete circuit is shown in figure 1. layout considerations to achieve accurate current sensing, a kelvin connection is recommended. the minimum trace width for 1oz cop- per foil is 0.02" per amp to make sure the trace stays at a reasonable temperature. using 0.03" per amp or wider is recommended. note that 1oz copper exhibits a sheet resistance of about 530 ? / . small resistances add up quickly in high current applications. to improve noise immunity, put the resistive divider to the uv, ov and fb pins close to the device and keep traces to v dd and gnd short. it is also important to put c3, the bypass capacitor for the intv cc pin, as close as possible between intv cc and gnd. a 0.1 f capacitor from the uv pin (and ov pin through resistor r2) to gnd also helps reject supply noise. figure 5 shows a layout that addresses these issues. note that a surge suppressor, z1, is placed be- tween supply and ground using wide traces. applicatio s i for atio wu uu sense ltc4260 v dd uv r1 sense resistor r s i load v in gnd i load r2 r3 r 8 c3 4260 f05 c f ov gnd intv cc fb z1 figure 5. recommended layout for r1, r2, r3, r8, c f , c3, z1 and r s
ltc4260 17 4260f applicatio s i for atio wu uu digital interface the ltc4260 communicates with a bus master using a 2-wire interface compatible with the i 2 c bus and the smbus, an i 2 c extension for low power devices. the ltc4260 is a read-write slave device and supports smbus bus read byte, write byte, read word and write word commands. the second word in a read word command will be identical to the first word. the second word in a write word command is ignored. the data formats for these commands are shown in figures 7 to10. using optoisolators with sda the ltc4260 separates the sda line into sdai and sdao. if optoisolators are not used then tie sdai and sdao together to construct a normal sda line. when using optoisolators connect the sdai to the output of the incom- ing opto and connect the sdao to the input of the out- going opto (see figure 13). start and stop conditions when the bus is idle, both scl and sda must be high. a bus master signals the beginning of a transmission with a start condition by transitioning sda from high to low while scl is high. when the master has finished commu- nicating with the slave, it issues a stop condition by transitioning sda from low to high while scl is high. the bus is then free for another transmission. i 2 c device addressing twenty-seven distinct bus address are configurable using the three-state adr0-adr2 pins. table 1 shows the correspondence between pin states and addresses. note that address bits b7 and b6 are internally configured to 10. in addition, the ltc4260 will respond to two special addresses. address (1011 111)b is a mass write used to write to all ltc4260, regardless of their individual address settings. the mass write can be masked by setting register bit a4 to zero. address (0001 100)b is the smbus alert response address. if the ltc4260 is pulling low on the alert pin, it will acknowledge this address using the smbus alert response protocol. acknowledge the acknowledge signal is used for handshaking between the transmitter and the receiver to indicate that the last byte of data was received. the transmitter always releases the sda line during the acknowledge clock pulse. when the slave is the receiver, it must pull down the sda line so that it remains low during this pulse to acknowledge receipt of the data. if the slave fails to acknowledge by leaving sda high, then the master can abort the transmis- sion by generating a stop condition. when the master is receiving data from the slave, the master must pull down the sda line during the clock pulse to indicate receipt of the data. after the last byte has been received the master will leave the sda line high (not acknowledge) and issue a stop condition to terminate the transmission. write protocol the master begins communication with a start condi- tion followed by the seven bit slave address and the r/w bit set to zero. the addressed ltc4260 acknowledges this and then the master sends a command byte which indi- cates which internal register the master wishes to write. the ltc4260 acknowledges this and then latches the lower three bits of the command byte into its internal register address pointer. the master then delivers the data byte and the ltc4260 acknowledges once more and latches the data into its internal register. the transmission is ended when the master sends a stop condition. if the master continues sending a second data byte, as in a write word command, the second data byte will be acknowl- edged by the ltc4260 but ignored. read protocol the master begins a read operation with a start condi- tion followed by the seven bit slave address and the r/w bit set to zero. the addressed ltc4260 acknowledges this and then the master sends a command byte that indicates which internal register the master wishes to read. the ltc4260 acknowledges this and then latches the lower three bits of the command byte into its internal register address pointer. the master then sends a repeated start condition followed by the same seven bit address with the
ltc4260 18 4260f r/w bit now set to one. the ltc4260 acknowledges and sends the contents of the requested register. the trans- mission is ended when the master sends a stop condi- tion. if the master acknowledges the transmitted data byte, as in a read word command, the ltc4260 will repeat the requested register as the second data byte. note that the register address pointer is not cleared at the end of the transaction. thus the receive byte protocol can be used to repeatedly read a specific register. alert response protocol the ltc4260 implements the smbus alert response protocol as shown in figure 11. if enabled to do so through the alert register b, the ltc4260 will respond to faults by pulling the alert pin low. multiple ltc4260s can share a common alert line and the protocol allows a master to determine which ltc4260s are pulling the line low. the master begins by sending a start bit followed by the special alert response address (0001 100)b with the r/w bit set to one. any ltc4260 that is pulling its alert pin low will acknowledge and begin sending back its individual slave address. an arbitration scheme ensures that the ltc4260 with the lowest address will have priority; all others will abort their response. the successful responder will then release its alert pin while any others will continue to hold their alert pins low. polling may also be used to search for any ltc4260 that have detected faults. any ltc4260 pulling its alert pin low will also release it if it is individually addressed during a read or write transaction. the alert signal will not be pulled low again until the fault register indicates a different fault has occurred or the original fault is cleared and it occurs again. note that this means repeated or continuing faults will not generate alerts until the associated fault register bit has been cleared. scl sda start condition stop condition address r/w ack data ack data ack 1 - 7 8 9 4260 f06 a6 - a0 b7 - b0 b7 - b0 1 - 7 8 9 1 - 7 8 9 p s figure 6. data transfer over i 2 c or smbus applicatio s i for atio wu uu
ltc4260 19 4260f applicatio s i for atio wu uu s address 1 0 a4:a0 4260 f07 from master to slave from slave to master a: acknowledge (low) a: not acknowledge (high) r: read bit (high) w: write bit (low) s: start condition p: stop condition command data x x x x x b2:b0 0 w 000 b7:b0 a a ap s address 1 0 a4:a0 command data data x x x x x b2:b0 0 w 000 0 4260 f08 x x x x x x x x b7:b0 a a a ap s address 1 0 a4:a0 1 0 a4:a0 1 0 command s address r a b7:b0 1 data x x x x x b2:b0 0 w 00 4260 f09 a a ap s address 1 0 a4:a0 1 0 a4:a0 1 0 command s address r a b7:b0 1 data x x x x x b2:b0 0 w 00 4260 f10 a 0 a b7:b0 data a ap s alert response address 0 0 0 1 1 0 0 device address 1 0 a4:a0 1 1 r 0 4260 f11 a a p figure 7. ltc4260 serial bus sda write byte protocol figure 8. ltc4260 serial bus sda write word protocol figure 9. ltc4260 serial bus sda read byte protocol figure 10. ltc4260 serial bus sda read word protocol figure 11. ltc4260 serial bus sda alert response protocol
ltc4260 20 4260f applicatio s i for atio wu uu table 1. ltc4260 i 2 c device addressing hex device ltc4260 description address binary device address address pins h 6 5 4 3 2 1 0 r/w adr2 adr1 adr0 mass write be 1 0 1 1 1 1 1 0 x x x alert response 19 0 0 0 1 1 0 0 1 x x x 0 80 1 00 0 0 00 x l nc l 1 82 1 00 0 0 01 x l h nc 2 84 1 00 0 0 10 x l nc nc 3 86 1 00 0 0 11 x l nc h 4 88 1 00 0 1 00 x l l l 5 8a 1 00 0 1 01 x l h h 6 8c 1 00 0 1 10 x l l nc 7 8e 1 00 0 1 11 x l l h 8 90 1 00 1 0 00 x nc nc l 9 92 1 00 1 0 01 x nc h nc 10 94 1 0 0 1 0 1 0 x nc nc nc 11 96 1 0 0 1 0 1 1 x nc nc h 12 98 1 0 0 1 1 0 0 x nc l l 13 9a 1001101x nc h h 14 9c 1001110x nc l nc 15 9e 1 0 0 1 1 1 1 x nc l h 16 a0 1010000x h nc l 17 a2 1010001x h h nc 18 a4 1010010x h nc nc 19 a6 1010011x h nc h 20 a8 1010100x h l l 21 aa 1010101x h h h 22 ac 1010110x h l nc 23 ae 1010111x h l h 24 b0 1011000x l h l 25 b2 1011001x nc h l 26 b4 1011010x h h l
ltc4260 21 4260f applicatio s i for atio wu uu table 2. ltc4260 register addresses and contents register register address* name read/write description 00h control (a) r/w controls whether the part retries after faults, set the switch state 01h alert (b) r/w controls whether the alert pin is pulled low after a fault is logged in the fault register 02h status (c) r system status information 03h fault (d) r/w fault log 04h sense (e) r/w** adc current sense voltage data 05h source (f) r/w** adc source voltage data 06h, 07h adin (g) r/w** adc adin voltage data *register address msbs b7-b3 are ignored. **writable if bit a5 set. table 3. control register a (00h)?ead/write bit name operation a7:6 gpio configure configures behavior of gpio pin a5 test mode enable test mode halts adc operation and enables writes to adc registers 1 = enable test mode, 0 = disable test mode (default) a4 mass write enable enables mass write using address (1011 111)b 1 = enable mass write (default), 0 = disable mass write a3 fet on control turns fet on and off 1 = turn fet on, 0 = turn fet off. defaults to on pin state at end of debounce delay a2 overcurrent autoretry enables autoretry after an overcurrent fault 1 = retry enabled, 0 = retry disabled (default) a1 undervoltage autoretry enables autoretry after an undervoltage fault 1 = retry enabled (default), 0 = retry disabled a0 overvoltage autoretry enables autoretry after an overvoltage fault 1 = retry enabled (default), 0 = retry disabled function a6 a7 gpio pin power good (default) 0 0 gpio = c3 power bad 0 1 gpio = c3 general purpose output 1 0 gpio = b6 general purpose input 1 1 gpio = hi-z
ltc4260 22 4260f applicatio s i for atio wu uu table 4. alert register b (01h)?ead/write bit name operation b7 reserved not used b6 gpio output output data bit to gpio pin when configured as output. defaults to 0 b5 fet short alert enables alert for fet short condition 1 = enable alert, 0 = disable alert (default) b4 bd_prst state change alert enables alert when bd_prst changes state 1 = enable alert, 0 = disable alert (default) b3 power bad alert enables alert when output power is bad 1 = enable alert, 0 = disable alert (default) b2 overcurrent alert enables alert for overcurrent condition 1 = enable alert, 0 = disable alert (default) b1 undervoltage alert enables alert for undervoltage condition 1 = enable alert, 0 = disable alert (default) b0 overvoltage alert enables alert for overvoltage condition 1 = enable alert, 0 = disable alert (default) table 5. status register c (02h)?ead only bit name operation c7 fet on indicates state of fet 1 = fet on, 0 = fet off c6 gpio input state of the gpio pin 1 = gpio high, 0 = gpio low c5 fet short present indicates potential fet short if current sense voltage exceeds 2mv while fet is off 1 = fet is shorted, 0 = fet is not shorted c4 board present indicates if a board is present when bd_prst is low 1 = bd_prst pin low, 0 = bd_prst pin high c3 power bad indicates power is bad when fb is low 1 = fb low, 0 = fb high c2 overcurrent indicates overcurrent condition during cool down cycle 1 = overcurrent, 0 = not overcurrent c1 undervoltage indicates input undervoltage when uv is low 1 = uv low, 0 = uv high c0 overvoltage indicates input overvoltage when ov is high 1 = ov high, 0 = ov low
ltc4260 23 4260f applicatio s i for atio wu uu table 6. fault register d (03h)?ead/write bit name operation d7:6 reserved d5 fet short fault occurred indicates potential fet short was detected when measured current sense voltage exceeded 2mv while fet was off 1 = fet was shorted, 0 = fet is good d4 board present changes state indicates that a board was inserted or extracted when bd_prst changed state 1 = bd_prst changed state, 0 = bd_prst unchanged d3 power bad fault occurred indicates power was bad when fb went low 1 = fb was low, 0 = fb was high d2 overcurrent fault occurred indicates overcurrent fault occurred 1 = overcurrent fault occurred, 0 = no overcurrent faults d1 undervoltage fault occurred indicates input undervoltage fault occurred when uv went low 1 = uv was low, 0 = uv was high d0 overvoltage fault occurred indicates input overvoltage fault occurred when ov went high 1 = ov was high, 0 = ov was low table 7. sense register e (04h)?ead/write bit name operation e7:0 sense voltage data v dd -sense current sense voltage data. 8-bit data with 300 v lsb and 76.8mv full scale table 8. source register f (05h)?ead/write bit name operation f7:0 source voltage data source pin voltage data. 8-bit data with 400mv lsb and 102.4v full scale table 9. adin register g (06h)?ead/write bit name operation g7:0 adin voltage data adin pin voltage data. 8-bit data with 10mv lsb and 2.56v full scale
ltc4260 24 4260f applicatio s i for atio wu uu 16 6 17 uv backplane plug-in card r3 2.05k 1% r2 1k 1% 4 5 10 9 8 11 7 2 1 24 23 18 13 20 14 12 19 15 r1 5.76k 1% v in 12v sda scl alert gnd v dd sense ltc4260gn intv cc adr0 adr1 nc adr2 r6 100k q1 si7880dp r s 0.003 ? r5 10 ? c1 22nf r7 6.65k 1% r8 2.94k 1% c t 0.68 f r4 100k c l 1000 f c3 0.1 f c f 0.1 f 25v gate gnd fb adin gpio bd_prst timer 4260 f12 source ov sdao sdai scl alert on + figure 12. 12a, 12v card resident application 16 6 17 uv backplane plug-in card r3 2.67k 1% r2 1.74k 1% 4 5 9 10 8 7 2 1 24 23 18 13 20 14 12 19 15 4260 f13 r1 49.9k 1% gnd v in C48v v dd sense ltc4260gn intv cc adr0 adr1 nc adr2 r6 100k q1 fdb3632 r s 0.01 ? r5 10 ? c1 6.8nf r7 43.7k 1% output r8 3.57k 1% c t 68nf c l 330 f 100v C48v c3 0.1 f c2 0.1 f q2 cmpta42 optional 5v r14 1k c f 0.1 f gate gnd fb adin gpio bd_prst timer source ov sdai sda0 scl on scl sda 3.3v moc207 moc207 moc207 C48v intv cc r9 10k intv cc intv cc r4 5.1k r12 10k r15 100 ? r13 3.4k r10 3.4k C48v figure 13. 3a, 48v card resident application
ltc4260 25 4260f u package descriptio gn package 24-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) .337 C .344* (8.560 C 8.738) gn24 (ssop) 0204 12 3 4 5 6 7 8 9 10 11 12 .229 C .244 (5.817 C 6.198) .150 C .157** (3.810 C 3.988) 16 17 18 19 20 21 22 23 24 15 14 13 .016 C .050 (0.406 C 1.270) .015 .004 (0.38 0.10) 45 0 C 8 typ .0075 C .0098 (0.19 C 0.25) .0532 C .0688 (1.35 C 1.75) .008 C .012 (0.203 C 0.305) typ .004 C .0098 (0.102 C 0.249) .0250 (0.635) bsc .033 (0.838) ref .254 min recommended solder pad layout .150 C .165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale
ltc4260 26 4260f u package descriptio sw package 24-lead plastic small outline (wide .300 inch) (reference ltc dwg # 05-08-1620) s24 (wide) 0502 note 3 .598 C .614 (15.190 C 15.600) note 4 22 21 20 19 18 17 16 15 1 23 4 5 6 78 .394 C .419 (10.007 C 10.643) 910 13 14 11 12 n/2 23 24 n .037 C .045 (0.940 C 1.143) .004 C .012 (0.102 C 0.305) .093 C .104 (2.362 C 2.642) .050 (1.270) bsc .014 C .019 (0.356 C 0.482) typ 0 C 8 typ note 3 .009 C .013 (0.229 C 0.330) .016 C .050 (0.406 C 1.270) .291 C .299 (7.391 C 7.595) note 4 45 .010 C .029 (0.254 C 0.737) .420 min .325 .005 recommended solder pad layout .045 .005 n 123 n/2 .050 bsc .030 .005 typ .005 (0.127) rad min inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. pin 1 ident, notch on top and cavities on the bottom of packages are the manufacturing options. the part may be supplied with or without any of the options 4. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm)
ltc4260 27 4260f u package descriptio information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693) 5.00 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 0.23 typ (4 sides) 31 1 2 32 bottom viewexposed pad 3.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh) qfn 0603 0.50 bsc 0.200 ref 0.00 C 0.05 0.70 0.05 3.45 0.05 (4 sides) 4.10 0.05 5.50 0.05 0.25 0.05 package outline 0.50 bsc recommended solder pad layout
ltc4260 28 4260f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2004 lt/tp 0904 1k ?printed in usa related parts part number description comments lt ? 1641-1/lt1641-2 positive high voltage hot swap controllers active current limiting, supplies from 9v to 80v ltc1921 dual C48v supply and fuse monitor withstands 200v, monitors under-/overvoltage and external fuses ltc2436 16-bit, 2-channel delta-sigma adc 800nv rms noise, two differential channels with automatic channel selection ltc4240 compactpci tm hot swap controller with i 2 c i/o 3.3v, 5v and 12v supplies, control and status over i 2 c lt4250 C48v hot swap controller in so-8 active current limiting, supplies from C20v to C80v ltc4252 C48v hot swap controller in msop fast active current limiting with drain accelerated response, supplies from C15v lt4256 positive 48v hot swap controller with foldback current limiting, open-circuit and overcurrent fault output, open-circuit detect up to 80v supply ltc4300a hot swappable 2-wire bus buffer provides capacitive buffering, sda and scl precharge and level shifting ltc4301 supply independent hot swappable 2-wire bus buffer provides capacitive buffering, sda and scl precharge and level shifting ltc4302 addressable 2-wire bus buffer provides capacitive buffering, sda and scl precharge and level shifting, enabled by 2-wire bus commands ltc4350 hot swappable load share controller output voltage: 1.2v to 12v, equal load sharing lt4351 ideal mosfet oring diode external n-channel mosfets replace oring diodes, 1.2v to 20v ltc4354 negative voltage diode-or controller 8-pin dfn and so package compactpci is a trademark of the pci industrial computer manufacturers group typical applicatio u uv 2.67k 1.74k 49.9k smat70b v dd sense ltc4260 100k fdb3632 0.01 ? 10 ? 6.8nf 43.5k v out 48v 3.57k 100k 0.1 f v in 48v gate intv cc adr0 adr1 nc adr2 gnd fb bd_prst timer adin gpio 4260 ta03 source ov on sdai sda0 scl alert 0.1 f 68nf 1 f backplane plug-in card load 3a, 48v backplane resident application with insertion activated turn-on

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